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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 1/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology features general description block diagram ? ieee802.3 and ieee802.3u compliant. ? provide 8 rmii (reduced media independent interface) ports. ? programmable 1k/8k mac addresses filtering. ? store and forward switching function and bad packet filtering function. ? optional back_pressure/802.3x flow control/ flooding control/broadcast control. ? optional eeprom interface for advanced switch configurations. ? 1mb/2mb sgram/sdram flexible memory interface. ? port vlan/trunking. ? link/rx activity, packet buffer utilization led display. ? 75mhz for non-blocking for 8 ports switch oper- ation ? build in internal/external memory test function. ? 160 pin pqfp package, 3.3v operation volt- age. 8 port 10m/100m ethernet switch the MTD508 complies fully with the ieee802.3, 802.3u and 802.3x specifications and is a non-blocking 8 port 10m/100m ethernet switch device. support 8 rmii ports for 10m/100m opera- tion. 1mbyte/2mbytes memory interface provides maximum 1365 packet buffers for ethernet packet buffering. up to 8192 address entrys are provided by the MTD508, and the MTD508 use full ethernet address compare algorithm to mini- mize hashing collision events. the MTD508 provides eeprom interface to config port trunking, port vlan, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. each MTD508 port support 10/100m auto-negotiation by mdc/mdio interface for connecting external phy devices. the MTD508 also provides 10 pins for link/rx activity, packet buffer utilization led dis- play function. sdram/ rmii7 port switch logic mac7 dma7 rmii4 mac4 dma4 rmii5 mac5 dma5 rmii6 mac6 dma6 rmii3 mac3 dma3 rmii0 mac0 dma0 rmii1 mac1 dma1 rmii2 mac2 dma2 memory arbiter memory controller sgram interface
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 2/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology system diagram MTD508 quad physceiver quad physceiver rmii0-3 rmii4-7 quad transformer quad transformer rj45 rj45 eeprom leds sgram (256k32x2) sgram (512k32x1) sgram (256k32x1) (**option) (**programmable) mii management
3/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 1.0 pin connection 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 l e d c l k 1 d q 0 d q 1 v c c i g n d i d q 2 d q 3 d q 4 d q 5 d q 6 d q 7 v c c o g n d o d q 1 6 d q 1 7 d q 1 8 d q 1 9 v c c i g n d i d q 2 0 v c c o g n d o d q 2 1 d q 2 2 d q 2 3 w e b c a s b r a s b c s 0 b b a v c c i g n d i c s 1 b a d 0 a d 1 a d 2 v c c i g n d i a d 3 a d 4 ledclk2 gndo vcco leddata7 leddata6 leddata5 leddata4 leddata3 leddata2 leddata1 leddata0 gndi clk25m vcci sdc sdio eeclk eedata resetb gndo refclk vcco mdio mdc gndi vcci crsdv0 txd0_1 txd0_0 txen0 gndi vcci rxd0_0 rxd0_1 crsdv1 txd1_1 txd1_0 txen1 rxd1_0 rxd1_1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 c r s d v 2 t x d 2 _ 1 t x d 2 _ 0 t x e n 2 g n d o v c c o r x d 2 _ 0 r x d 2 _ 1 c r s d v 3 t x d 3 _ 1 t x d 3 _ 0 t x e n 3 r x d 3 _ 0 r x d 3 _ 1 c r s d v 4 c o l 4 t x d 4 _ 3 t x d 4 _ 2 t x d 4 _ 1 t x d 4 _ 0 t x e n 4 t x c 4 r x c 4 r x d v 4 g n d i v c c i r x d 4 _ 0 r x d 4 _ 1 r x d 4 _ 2 r x d 4 _ 3 c r s d v 5 t x d 5 _ 1 t x d 5 _ 0 t x e n 5 r x d 5 _ 0 r x d 5 _ 1 c r s d v 6 t x d 6 _ 1 t x d 6 _ 0 t x e n 6 MTD508 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 vcco gndo ad5 ad6 ad7 ad8 vcci memclk gndi dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq24 dq25 dq26 vcco gndo dq27 dq28 dq29 dq30 dq31 vcci sysclk gndi rxd7_1 rxd7_0 vcci gndi txen7 txd7_0 txd7_1 crsdv7 rxd6_1 rxd6_0
4/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 2.0 pin descriptions rmii port interface pins name pin number i/o descriptions crsdv0 147 i port0 rmii receive interface signal, crsdv0 is asserted high when port0 media is non_idle. rxd0_0 rxd0_1 153 154 i i port0 rmii receive data bit_0. port0 rmii receive data bit_1. txen0 150 o port0 rmii transmit enable signal. txd0_0 txd0_1 149 148 o o port0 rmii transmit data bit_0. port0 rmii transmit data bit_1. crsdv1 155 i port1 rmii receive interface signal, crsdv1 is asserted high when port1 media is non_idle. rxd1_0 rxd1_1 159 160 i i port1 rmii receive data bit_0. port1 rmii receive data bit_1. txen1 158 o port1 rmii transmit enable signal. txd1_0 txd1_1 157 156 o o port1 rmii transmit data bit_0. port1 rmii transmit data bit_1. crsdv2 01 i port2 rmii receive interface signal, crsdv2 is asserted high when port2 media is non_idle. rxd2_0 rxd2_1 07 08 i i port2 rmii receive data bit_0. port2 rmii receive data bit_1. txen2 04 o port2 rmii transmit enable signal. txd2_0 txd2_1 03 02 o o port2 rmii transmit data bit_0. port2 rmii transmit data bit_1. crsdv3 09 i port3 rmii receive interface signal, crsdv0 is asserted high when port3 media is non_idle. rxd3_0 rxd3_1 13 14 i i port3 rmii receive data bit_0. port3 rmii receive data bit_1. txen3 12 o port3 rmii transmit enable signal. txd3_0 txd3_1 11 10 o o port3 rmii transmit data bit_0. port3 rmii transmit data bit_1. crsdv4 15 i port4 rmii/mii receive interface signal, crsdv4 is asserted high when port4 media is non_idle. rxdv4 24 i port4 mii receive data valid. in rmii mode, this pin don?t use. rxclk4 23 i port4 mii receive clock signal. in rmii mode, this pin is not used. rxd4_3 rxd4_2 rxd4_0 rxd4_1 30 29 27 28 i i i i port4 mii receive data bit_3. in rmii mode, this pin don?t use. port4 mii receive data bit_2. in rmii mode, this pin don?t use. port4 rmii/mii receive data bit_0. port4 rmii/mii receive data bit_1. txen4 21 o port4 rmii transmit enable signal. txclk4 22 i port4 rmii transmit clock signal. in rmii mode, this pin is not used.
5/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology txd4_3 txd4_2 txd4_0 txd4_1 17 18 20 19 o o o o port4 mii transmit data bit_3. in rmii mode, this pin don?t use. port4 mii transmit data bit_2. in rmii mode, this pin don?t use. port4 rmii/mii transmit data bit_0. port4 rmii/mii transmit data bit_1. col4 16 i port4 mii collision input. in rmii mode, this pin don?t use. clk25m 155 o port4 mii 25mhz clock output. crsdv5 31 i port5 rmii receive interface signal, crsdv5 is asserted high when port5 media is non_idle. rxd5_0 rxd5_1 35 36 i i port5 rmii receive data bit_0. port5 rmii receive data bit_1. txen5 34 o port5 rmii transmit enable signal. txd5_0 txd5_1 33 32 o o port5 rmii transmit data bit_0. port5 rmii transmit data bit_1. crsdv6 37 i port6 rmii receive interface signal, crsdv6 is asserted high when port6 media is non_idle. rxd6_0 rxd6_1 41 42 i i port6 rmii receive data bit_0. port6 rmii receive data bit_1. txen6 40 o port6 rmii transmit enable signal. txd6_0 txd6_1 39 38 o o port6 rmii transmit data bit_0. port6 rmii transmit data bit_1. crsdv7 43 i port7 rmii receive interface signal, crsdv7 is asserted high when port7 media is non_idle. rxd7_0 rxd7_1 49 50 i i port7 rmii receive data bit_0. port7 rmii receive data bit_1. txen7 46 o port7 rmii transmit enable signal. txd7_0 txd7_1 45 44 o o port7 rmii transmit data bit_0. port7 rmii transmit data bit_1. sgram/sdram interface pins name pin number i/o descriptions ad[8:0] 75,76,77,78, 81,82,85,86, 87 o memory row/column address bus outputs ad[7:0] are row/column address [7:0]. ad[8] : this pin should connect to sgram/sdram msb address bit. dq[31:0] 54~58,61~71 ,96~98,101, 104~107,110 ~115,118, 119 i/o memory data bus rasb 93 o sgram/sdram row address select casb 94 o sgram/sdram column address select web 95 o sgram/sdram write enable rmii port interface pins name pin number i/o descriptions
6/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology note: sgram/sdram access time: 10 ns (max) ba 91 o sgram/sdram bank select cs0b 92 o memory chip select 0 cs1b 88 o memory chip select 1 memclk 73 o memory clock output. led interface pins name pin number i/o descriptions leddata [7:0] 124,125,126, 127,128,129, 130,131 i/o led data output. these led pins report port0~7 link/rx activity status using ledclk1 strobe , and report packet buffer utilization status using ledclk2 strobe. leddata [0] [1] [2] [3] [4] [5] [6] [7] ledclk1 lr0 lr1 lr2 lr3 lr4 --- --- --- ledclk2 uti0 uti1 uti2 uti3 uti4 --- bfull mfail note: lrn: means per port?s link_rxact status. uti0: 5%, uti1: 10%, uti2: 20%, uti3: 35%, uti4: 50 above . bfull: buffer almost full alarm signal. mfail: external memory power on test failure. ledclk1 120 i/o led strobe 1 ledclk2 121 i/o led strobe 2 miscellaneous pins name pin number i/o descriptions resetb 139 i system reset input, low active. sysclk 52 i switch core system clock input, using 75 mhz. refclk 141 i rmii reference clock input, using 50mhz. mdc 144 i/o mii management clock inout mdio 143 i/o mii management data inout sdc 135 i/o mii register clock inout sdio 136 i/o mii register data inout eedata 138 i/o eeprom data input eeclk 137 i/o eeprom clock output sgram/sdram interface pins name pin number i/o descriptions
7/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology vcc 06,26,48,53, 60,74,80,84, 90,100,103, 109,117,123, 134,142,146, 152 pwr power pins gnd 05,25,47,51, 59,72,79,83, 89,99,102, 108,116,122, 132,140,145, 151 gnd ground pins miscellaneous pins name pin number i/o descriptions
8/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology jummper configuration after power on reset name pin number i/o descriptions leddata[0] leddata[1] leddata[2] leddata[3] leddata[4] leddata[5] leddata[6] leddata[7] i/o during power on reset duration, these pins are jumper setting pins (pull_hgih = 1, pull_low = 0). leddata[0] : select sgram/sdram interface , ?1? means 256k32 x 1 or 512k32 x 1 is selected. ?0? means 256k32 x 2 is selected, default is ?1?. leddata[1] : config packet buffer size, ?1? means 2 m bytes buffer size is selected. ?0? means 1 m byte buffer size is selected, default is ?0? leddata[2] : enable memory test function, ?1? means enable. ?0? means disable, default is ?1?. leddata[3] : enable aging function, ?1? means enable. ?0? means disable, default is ?1?. leddata[4] : enable mii polling(mdc/mdio), ?1? means enable. ?0? means disable, default is ?1?. leddata[5] : enable broadcast storm control, ?1? means enable. ?0? means disable, default is ?1?. leddata[6] : enable backpressure function (in half mode), ?1? means enable. ?0? means disable, default is ?1?. leddata[7] : enable 802.3x flow control function (in full mode) , ?1? means enable. ?0? means disable, default is ?1?. ledclk1 i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). ledclk1 : select 1k or 8k address entry table, ?1? means 8k addres entry is selected. ?0? means 1k address entry is selected, default is ?1?. ledclk2 i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). ledclk2 : enable eeprom interface, ?1? means enable. ?0? means disable, default is ?1?.
9/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology eedata i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). eedata : enable eeprom auto_load configuration function while eeprom interface is enabled, ?1? means enable. ?0? means disable, default is ?1?. txen[2:0] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[2:0] : uplink port (flooding port) 0 ~7 selection; default is ?000?. txen[3] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[3] : enable flooding control, ?1? means enable. ?0? means disable, default is ?0?. txen[4] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[4] : enable vlan tag 1522 bytes receiving, ?1? means enable. ?0? means disable, default is ?0?. txen[5] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[5] : select port7 full/half ability while port7 in fx mode, ?1? means port7 full duplex is selected. ?0? means port7 half duplex is selected, default is ?0?. txen[7] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[7] : enable port7 fx mode, ?1? means enable. ?0? means disable, default is ?0?. sdc i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). sdc : port4 mii/rmii interface selection, ?1? means port4 mii interface is selected; in the mean time, port5,6,7 will automatically be disable. ?0? means port4 rmii interface is selected, default is ?0?. jummper configuration after power on reset name pin number i/o descriptions
10/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology eeclk i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). eeclk : scan mode enable for debugging purpose, ?1? means scan mode enable. ?0? means scan mode disable, default is ?0?. mdc i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). mdc : fast mode enable for testing purpose, ?1? means fast mode enable. ?0? means fast mode disable, default is ?0?. jummper configuration after power on reset name pin number i/o descriptions
11/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 3.0 functional descriptions the MTD508 is an 8 ports 10/100 mbps fast ethernet switch controller. it is a low cost solution for eight ports fast ethernet soho switch design. no cpu interface is required; after power on reset, MTD508 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device, and MTD508 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc functions. the follow- ing descriptions are MTD508?s major functional blocks overview. 3.1 packet store and forwarding the MTD508 use simple store and forward algorithm as packet switching method. input packet from ports will be stored to external memory first, while packet is good for forward (crc chech ok, 64bytes < length < 1518bytes, not local packets, in the same vlan group ) , if this packet?s da hits, than forward this packet to the destination port, otherwise this packet will be broadcasted. 3.2 learning and routing the MTD508 supports 1k or 8k mac entries for switching. dynamic address learning is performed by each good unicast packet is completely received. the static address learning is achieved by eeprom configuration. on the other hand, the routing process is performed whenever the packet?s da is cap- tured. if the da can not get a hit result, the packet is going to switch broadcast or forward to the dedi- cated port according to the flooding control selction. 3.3 aging only the dynamic address entries are scheduled in the aging machine. if one station does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time can be program through the eeprom auto load configuration. (default value is 300 seconds) 3.4 buffer queue management the buffer queue manager is implemented to manage the external shared memory (use sdram/ sgram) for packet buffering. the main function of the buffer queue manager is to maintain the linked list consists of buffer ids, which is used to show the corresponding memory address for each incoming packet. in addition, the buffer queue manager monitors the rested free spaces status of the external memory, if the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission id queue overflow happening. MTD508 provide 802.3x flow control in full duplex mode and back pressure control in half duplex mode. 3.5 full duplex 802.3x flow control in full duplex mode, MTD508 supports the standard flow control defined in ieee802.3x standard. it enables the stopping of remote node transmissions via a pause frame information interactoin. when the ?802.3x flow control enable? bit is set during power on reset (leddata[7] pin is external pull_high), it enables MTD508 supporting 802.3x flow control function in full_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value (recommended xon_th = 74?h when using 2mbytes external memory; xon_th = 2e?h when using 1mbytes external memory), MTD508 will send out a pause packet with pause time equal to fff to stop the remote node transmis- sion; when the output port buffer queue?s on_using value reduce to the initialization threshold value(recommended xoff_th = 30?h when using 2mbytes external memory; xoff_th=18?h when using 1mbytes external memory), MTD508 will also send a pause packet with pause time equal to zero to inform the remote node to retransmit packet.
12/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 3.6 half duplex back pressure control in half duplex mode, MTD508 provide a back pressure control mechanism to avoid dropping packets during network conjection situation. when the ?back pressure control enable? bit is set during power on reset (leddata[6] pin is external pull_high), it enables MTD508 supporting back pressure function in half_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value (same with the xon_th value), MTD508 will send a jam pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. if the ?back pressure control enable? bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. 3.7 mii polling the MTD508 supports phy management through the serial mdio/mdc interface. after power on reset, the MTD508 write related abilities to the advertisement register 4 of connected phy devices and restart the auto_negotiation prcedure via mdio/mdc interface using the predefined phy addresses increasingly from ?01000?b to ?01111?b. the MTD508 will periodically and continuously poll and update the link status and link partner?s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected phy devices through mdio/mdc serial interface. 3.8 mac and dma engine the MTD508?s mac performs all the functions in ieee802.3 protocol, such as frame formatting, frame stripping, crc checking, bad packet dropping, defering to line traffic, and collision handling. the mac rx_engine checks incoming packets and drops the bad packet which include crc error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the ?vlan tag 1522 bytes receive enable? bit is set during power on reset). before transmission, the mac tx_engine will constantly monitor the line traffic using derfering precedure. only if it has been idle for a 96 bits time (a minimum interpacket gap time, ipg time), actual transmmission can be started. for the half duplex mode, mac engine will detect collision; if a collision is detected, the mac tx_engine will transmit a jam pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (MTD508 implements the truncated exponential back_off algorithm defined in ieee 802.3 standard). for the full duplex mode, collision signal is ignored. the MTD508?s dma engine performs the packets non_blocking transportation between mac engine and external memory according to a high speed switching procedure. the switching procedure is com- pleted by address learning/routing process and buffer queue management operation. 3.9 eeprom interface MTD508 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device(24c02) after power on reset . MTD508 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc functions. the following table is the eeprom contents mapping: name eeprom address eeprom content description recommended value under basic operation eob 00 last eeprom content address value 8?h13 agelow 01 aging time bit [7:0] 8?h2c agehigh 02 aging time bit [15:8] 8?h01 vlan0 03 port0 vlan register 8?hfe vlan1 04 port1 vlan register 8?hfd vlan2 05 port2 vlan register 8?hfb vlan3 06 port3 vlan register 8?hf7 vlan4 07 port4 vlan register 8?hef
13/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology vlan5 08 port5 vlan register 8?hdf vlan6 09 port6 vlan register 8?hbf vlan7 0a port7 vlan register 8?h7f uplink10 0b bit[7:4] --- the flooding port_no of port1 bit[3:0] --- the flooding port_no of port0 *ex1: bit[7:4] = ?0011?b, means that if the incomin packet of port1 got the ?un_routed? result, then this incoming packet will be flooded to port3. *ex2: bit[3:0] = ?0111?b, means that if the incomin packet of port0 got the ?un_routed? result, then this incoming packet will be flooded to port7. (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h0f uplink32 0c bit[7:4] --- the flooding port_no of port3 bit[3:0] --- the flooding port_no of port2 (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h00 uplink54 0d bit[7:4] --- the flooding port_no of port5 bit[3:0] --- the flooding port_no of port4 (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h00 uplink76 0e bit[7:4] --- the flooding port_no of port7 bit[3:0] --- the flooding port_no of port6 (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h00 broadcast th 0f broadcast threshold 8?hff xon th 10 xon threshold 8?h74 xoff th 11 xoff threshold 8?h30 disport 12 disable port 8?h00 system control 13 system control byte : bit[0] --- enhanced back pressure enable, bit[7:1] --- reserved. 8?h00 reserved 14 ~1f none staticsa1 20 ~26 address 26 bit[2:0] --- means port id address 25 bit[7:0] ~ address 20 bit[7:0] --- means static sa[47:0] staticsa2 27 ~ 2d address 2d bit[2:0] --- means port id address 2c bit[7:0] ~ address 27 bit[7:0] --- means static sa[47:0] name eeprom address eeprom content description recommended value under basic operation
14/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 3.10 port based vlan the MTD508 supports vlan configuration by port based methodology. one port select the certain ports to form its vlan group by configuring the vlan register. the packet (including broadcast packet) is not forwarding to the destination port whose vlan group is different from the source port. 3.11 port trunking the port trunking function can also be implemented by vlan registers. one trunk port isolates the packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology. the non-trunk port should choose only one trunk port for transmitting, which can achieve the load bal- ancing and maintain the packet sequences. 3.12 memory interface two kinds of external memory interface can be selected by user -- 1m byte memory (256k32 x 1) and 2 m bytes (256k32 x 2 or 512k32 x 1). maximum 2m byte external memory can be used for packet buff- ering. ?-10 ? speed grade of sgram/sdram device is recommanded. the following table is the sgram application pin connection : 3.13 internal mii registers acess and control the MTD508 support 2 serial pins (sdio/sdc) for internal registers acess and control; the detailed registers informations are presented in section4.0 (internal mii registers). 3.14 led display the MTD508 use 10 pins to output 2 kinds of led display -- leddata[7:0], ledclk1, ledclk2. using ledclk1 rising edge, leddata[7:0] report port7~0 link/receive activity led status. using ledclk2 rising edge, leddata[4:0] report packet buffer utilization rating, and leddata[7] report external memory test result(after power reset, MTD508 will test external sdram automatically), led- data[6] report the buffer almost full alarm signal . memory type memory chip no a[8] cs0b cs1b 256k32 x 1 a8 cs0b nc 256k32 x 2 a8 cs0b cs1b 512k32 x 1 a9 cs0b a8
15/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 4.0 internal mii registers the MTD508 implements 10 mii global registers and 4 per port registers, define as following tables: table 1. mii registers global registers reg no bits name r/w descriptions default 0 ctlreg0 r/w control register 0 8-0 bit[0] = 1 --> switch to port 0 registers bit[1] = 1 --> switch to port 1 registers bit[2] = 1 --> switch to port 2 registers bit[3] = 1 --> switch to port 3 registers bit[4] = 1 --> switch to port 4 registers bit[5] = 1 --> switch to port 5 registers bit[6] = 1 --> switch to port 6 registers bit[7] = 1 --> switch to port 7 registers bit[8] = 1 --> switch to global registers 9?h100 12-9 scan mode select 3-0 15-13 scan port select 1 ctlreg1 r/w control register 1 16?h3084 7-0 xon xon threshold. 15-8 xoff xoff threshold. while eeprom is enabled, this register?s content will be updated by eeprom read xon/xoff threshold data automatically. after eeprom read is done, this register can be read/write by management cmd. default is 16?h3084(2m memory) or 16?h1838(1m mem- ory) 2 ctlreg2 r/w control register 2 16?d300 15-0 aging bit[15:0] can specify aging time. while eeprom is enabled, this register?s content will be updated by eeprom read aging timer data auto- matically. after eeprom read is done, this register can be read/write by management cmd. 3 ctlreg3 r/w control register 3 16?h000f 15-0 uplink reg0 bit[15:12] specify port 3?s uplink port id. bit[11:8] specify port 2?s uplink port id. bit[7:4] specify port 1?s uplink port id. bit[3:0] specify port 0?s uplink port id. default is 16?h000f. p.s this register?s write sequence is jumper setting ==> eeprom content ==> mii management command. 4 ctlreg4 r/w control register 4 16?h0
16/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 15-0 uplink reg1 bit[15:12] specify port 7?s uplink port id. bit[11:8] specify port 6?s uplink port id. bit[7:4] specify port 5?s uplink port id. bit[3:0] specify port 4?s uplink port id. default is 16?h0. p.s this register?s write sequence is jumper setting ==> eeprom content ==> mii management command. 5 ctlreg5 r/w control register 5 16?hff 7-0 bit[7:0] specify broadcast threshold. 8 bit[8] enable enhance backpressure. 15-9 reserved. p.s this register can be writed by eeprom content or mii management command too. 6 stsreg0 ro/ rc status register 0 7-0 bit[7:0] outputs port7-0 rxdma fifofull. 15-8 bit[15:8] outputs port7-0 txdma tpur(fifoempty). 7 stsreg1 ro status register 1 0 bufbistdone. 1 bufbisterr. 2 bufinitdone. 3 addrtblbistdone. 4 addrtblbisterr. 5 lthtblbistdone. 6 lthtblbisterr. 7 membistdone. 8 membisterr. 9 eedone. 10 freecntis0. 15-11 reserved. 8 ctlreg7 r/w control register 7 7-0 bit[7:0] output mii polling port7-0 flow control information 15-8 bit[15:8] output mii polling port7-0 link information "1" means flow control enable or link good. 9 ctlreg8 r/w control register 8 7-0 bit[7:0] output mii polling port7-0 speed information 15-8 bit[15:8] output mii polling port7-0 full information "1" means 100m or full duplex. port registers table 1. mii registers global registers reg no bits name r/w descriptions default
17/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology "r/w" means read/writable. 1 stsreg1 ro status register 1 10-0 bit[10:0] output port tx queue head value. 15-11 reserved. 2 stsreg2 ro status register 2 10-0 bit[10:0] output port tx queue tail value. 15-11 reserved. 3 stsreg3 ro status register 3 10-0 bit[10:0] output port tx queue count value. 15-11 reserved. 4 ctlreg1 r/w control register 1 7-0 bit[7:0] select port vlan group. 15-8 reserved. table 1. mii registers global registers reg no bits name r/w descriptions default
18/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 5.0 electrical characteristics 5.1 absolute maximum ratings 5.2 recommended operating conditions 5.3 dc electrical characteristics (under recommended operating conditions and vcc = 3.0 ~ 3.6v, tj = 0 to +115 o c) symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - vcc v t j commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-direction buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 0.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 2.4 v r i input pull-up/down resistance v il =0v or v ih =v cc 75 kohm
19/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 5.4 electrical characteristics symbol parameter min. typ. max. unit note t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns symbol parameter min. typ. max. unit note t5 mii input setup time 10 ns t6 mii input hold time 10 ns t7 mii output setup time 3 ns t8 mii output hold time 5 ns figure 1. rmii timing refclk crsdv txen txd[1:0] rxd[1:0] t1 t2 t3 t4 valid valid figure 2. mii timing rxclk0 crs0/rxdv0 txen0 txd0[3:0] rxd0[3:0] t5 t6 t7 t8 valid valid txclk0
20/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology symbol parameter min. typ. max. unit note t5 memory clock cycle 12 ns t6 memory command/address/data setup time 6 ns t7 memory command/address/data hold time 2 ns t8 row active to burst write 2 clk figure 3. memory write timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[31:0] valid t6 t7 t8 web memclk t6 t7 t6 t7 figure 4. memory read timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[31:0] valid t6 t7 t8 web memclk t6 t7 t9 t10
21/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology symbol parameter min. typ. max. unit note t10 memory read data setup time 2 ns t11 memory ead data hold time 2 ns symbol parameter min. typ. max. unit note t11 eeprom clock cycle 10 us t12 eedata input setup time 1 ns t13 eedata input hold time 1 ns symbol parameter min. typ. max. unit note t14 led display strobe period 20 us t15 ledclk setup time 5 us t16 ledclk hold time 5 us figure 5. eeprom timing eeclk t11 t13 eedata valid t12 figure 6. led interface ledclk2 t16 leddata valid t15 ledclk1 valid valid t14
22/22 MTD508 revision 1.2 14/04/2000 MTD508 (preliminary) myson technology 6.0 160 pin pqfp package data 1 40 41 80 81 120 121 160 seating plane see detail a a a 2 a 1 e b h d d h e e l l1 c a1 detail : ?a? note: dimension d & e do not include resin burrs gate stubs. symbol dimension in inch dimemsion in mm a 0.145(max) 3.683(max) a1 0.127+/-0.005 3.226+/-0.127 a2 0.006+0.004 -0.002 0.152+0.102 -0.051 b 0.012(ref) 0.300(ref) c 0.006+0.004 -0.002 0.152+0.102 -0.051 d 1.102+/-0.005 28.000+/-0.127 e 1.102+/-0.005 28.000+/-0.127 e 0.026+/-0.006 0.650+/-0.152 h d 1.228+/-0.012 31.200+/-0.300 h e 1.228+/-0.012 31.200+/-0.300 l 0.034+/-0.008 0.867+/-0.203 l1 0.063+/-0.008 1.600+/-0.203 y 0.003(max) 0.076(max) a1 0 o ~ 7 o 0 o +/- 7 o a2 7 o +/- 2 o 7 o +/- 2 o a2

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